1. Field of the Invention
The present invention relates to a method for fabricating a MOSFET device and, more particularly, to a method for fabricating a MOSFET capable of forming an ultra shallow junction and improving the stability of threshold voltage control.
2. Description of the Related Art
As is well known, gates of MOSFET devices are typically made from polysilicon. This is because polysilicon provides the properties required for gates, for example, high melting point, easy formation of thin films, easy patterning of lines, stability in an oxidizing atmosphere, and suitability for the formation of planarized surfaces. Where such polysilicon gates are employed in MOSFET devices, the resistance is typically lowered by doping the polysilicon with a dopant such as phosphorous (P), arsenic (As), or boron (B).
Meanwhile, the increased degree of integration of MOSFET devices requires corresponding reductions in the values of various parameters, such as the line width of gates, the thickness of gate insulating films, and/or the junction depth in those MOSFET devices. For this reason, where highly integrated MOSFET devices are fabricated using polysilicon gates, it is difficult to achieve the desired low resistance while also achieving the required micro line width. Thus, it is necessary to develop gates made of a material after than doped for polysilicon.
At the early stage of this development, active research and development efforts have been made in connection with polycide gates employing a transition metal-silicide material.
However, such polycide gates are limited in their ability to provide low resistance gates due to the fact that polysilicon still remains in the electrode structure. That is, polycide gates have problems such as increasing the effective thickness of gate insulating film due to a gate depletion effect and introducing variations in the threshold voltage as a result of boron penetration and dopant distribution fluctuations in P+ polysilicon gates.
As a result, active research and development efforts have recently become more focused on metal gates. The metal gates solve the above mentioned problems involved in the polycide gates because they do not use any dopant. Also, where such a metal gate comprises a metal having a work function value corresponding to the mid band-gap of silicon, it can be fabricated into gates usable for both NMOS and PMOS type devices. Metals having a work function value corresponding to the mid band-gap of silicon may include tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), molybdenum (M), tantalum (Ta), and tantalum nitride (TaN).
Where such a metal gate is actually employed in a MOSFET device, however, it introduces problems associated with the required processing, such as etching difficulties damage generated by plasma during the etching process and ion implantation, and/or thermal damage resulting from thermal processes subsequent to the formation of the gate that tend to degrade device characteristics.
For this reason, it is difficult to form such a metal gate using conventional gate formation processes. To this end, a method has been proposed in which the metal gates are formed using a damascene process. The metal gate formation method using the damascene process involves sequential formation of a transistor including a sacrificial gate made of polysilicon, formation of an interlayer insulating film, removal of the sacrificial gate, deposition of metal film, and a chemical mechanical polishing (CMP) process for the metal film.
Since this metal gate formation method process involves no etching processes, it has advantages of avoiding etch-induced degradation in the characteristics of the device. Moreover, the method can integrated easily into a conventional MOSFET process by selecting the metal suitable for CMP processing.
A conventional MOSFET fabrication method using a damascene process will be described in conjunction with FIGS. 1A to 1H.
Referring to FIG. 1A, a silicon substrate 1 is first prepared which has field oxide films 2 defining an active region. A first thermal oxide film 3 is formed as a screen oxide film on the silicon substrate 1 to cover the active region. Thereafter, desired impurity ions are implanted to control threshold voltage into the silicon substrate 1 through the first thermal oxide film 3.
Referring to FIG. 1B, the first thermal oxide film is removed, and a oxide film 4 is then formed on the silicon substrate 1. A polysilicon film 5 is deposited on the filed oxide film 2 and the oxide film 4. A hard mask film 6 of oxide film or nitride film is then deposited on the polysilicon film 5.
Referring to FIG. 1C, a hard mask pattern 6a is formed by patterning the hard mask film in accordance with a conventional photolithography process. The polysilicon film and the oxide film 4 are then etched using the hard mask pattern 6a as an etch mask to form a sacrificial gate 5a. A gate re-oxidation process is conducted on the resultant structure to remove the etch damage from the silicon substrate 1 and prevent it from further damage during the subsequent implantation process. As a result of this reox process, a second thermal oxide film 11 is formed on the side walls of the sacrificial gate 5a and the exposed surfaces of the silicon substrate 1.
Referring to FIG. 1D, impurity ions having a desired conductivity are implanted in a low concentration into portions of the silicon substrate 1 on opposite sides of the sacrificial gate 5a, thereby forming a lightly doped drain LDD region 12.
Referring to FIG. 1E, the second thermal oxide film is removed. A nitride film is deposited on the entire resultant structure and then the nitride film is blanket etched, thereby forming a spacer 13 on the side walls of the sacrificial gate 5a and the hard mask pattern 6a. Impurity ions having a desired conductivity are then implanted in a high concentration into portions of the silicon substrate on opposite sides of the sacrificial gate 5a including the spacer 13, thereby forming source/drain regions 14.
Referring to FIG. 1F, an interlayer insulating film is deposited on the resultant structure. The interlayer insulating film 15 and the hard mask pattern 6a are polished by employing a CMP process using the sacrificial gate 5a as a polishing stop layer. As a result, the interlayer insulating film 15 is planarized, the hard mask pattern is removed, and the sacrificial gate 5a is exposed.
Referring to FIG. 1G, the exposed sacrificial gate is removed, thereby forming a groove defining a region where a metal gate is to be formed. A gate insulating film 16 is then formed on the resultant structure. A metal film 17 is then deposited to a thickness at least sufficient to fill the groove completely.
Referring to FIG. 1H, a metal gate 20 is then formed by polishing the metal film in accordance with a CMP process using the interlayer insulating film 15 as a polishing stop layer, thereby completing a MOSFET device having a metal gate 20.
However, in accordance with a conventional MOSFET fabrication method, it is difficult to form an ultra shallow junction required in a high integrated MOSFET device. For this reason, it is necessary to use a process technique capable of forming elevated source/drain regions. Moreover, there is a disadvantage that tends to produce unstable MOSFET threshold voltages because the impurity ions implanted for controlling threshold voltage have a varied distribution after the thermal processing.
Therefore, it is an object of the present invention to provide a MOSFET device fabrication method capable of forming an ultra shallow junction and ensuring the stability of the threshold voltage.
In accordance with the present invention, this object is accomplished by providing a method for fabricating a MOSFET device comprising the steps of preparing a silicon substrate provided with field oxide films; forming a oxide film and a polysilicon film on the silicon substrate; forming a hard mask pattern defining a gate formation region on the polysilicon film; forming a sacrificial gate by etching the polysilicon film and the oxide film using the hard mask pattern as an etch mask; forming a thermal oxide film on the side walls of the sacrificial gate and the exposed surface of silicon substrate by a re-oxidation process; forming LDD regions in the silicon substrate at opposite sides of the sacrificial gate by implanting impurity ions having a desired conductivity using the sacrificial gate as an ion implantation mask; removing the thermal oxide film; forming a spacer on the side walls of the sacrificial gate and the hard mask pattern; forming source/drain regions in portions of silicon substrate on at opposite sides of the sacrificial gate by implanting impurity ions having a desired conductivity using the sacrificial gate and the spacer as an ion implantation mask; depositing an interlayer insulating film on the resultant structure; removing a portion of the interlayer insulating film and the hard mask pattern to expose the sacrificial gate and planarize the structure; removing the exposed sacrificial gate to form a groove exposing that portion of silicon substrate that had been under the sacrificial gate; etching the exposed portion of silicon substrate to a desired thickness; forming a sacrificial oxide film on the etched surface of silicon substrate; implanting impurity ions for controlling threshold voltage into the silicon substrate through the sacrificial oxide film; removing the sacrificial oxide film; forming a gate insulating film on the resultant structure; depositing a desired metal film on the gate insulating film sufficient to fill the groove completely; and forming a metal gate by etching the metal film and the gate insulating film until the interlayer insulating film is exposed.